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1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2011. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. 1.2a high efficiency buck-boost regulators isl9110, isl9112 the isl9110 and isl9112 are highly-integrated buck-boost switching regulators that accept input voltages either above or below the regulated output voltage. unlike other buck-boost regulators, these regulators au tomatically transition between operating modes without sign ificant output disturbance. both parts are capable of delivering up to 1.2a output current, and provide excellent efficiency due to their fully synchronous 4-switch architecture. no-load quiescent current of only 35a also optimizes efficiency under light-load conditions. forced pwm and/or synchronization to an external clock may also be selected for noise sensitive applications. the isl9110 is designed for standalone applications and supports 3.3v and 5v fixed output voltages or variable output voltages with an external resistor divider. output voltages as low as 1v, or as high as 5.2v are supported using an external resistor divider. the isl9112 supports a broader set of programmable features that may be accessed via an i 2 c bus interface. with a programmable output voltage range of 1.9v to 5v, the isl9112 is ideal for applications requiring dynamically changing supply voltages. a programmable slew rate can be selected to provide smooth transitions between output voltage settings. the isl9110 and isl9112 require only a single inductor and very few external components. power supply solution size is minimized by a tiny 3mmx3mm package and a 2.5mhz switching frequency, which further reduces the size of external components. features ? accepts input voltages above or below regulated output voltage ? automatic and seamless transitions between buck and boost modes ? input voltage range: 1.8v to 5.5v ? output current: up to 1.2a ? high efficiency: up to 95% ? 35a quiescent current maxi mizes light-load efficiency ? 2.5mhz switching frequency mi nimizes external component size ? selectable forced-pwm mode and external synchronization ?i 2 c interface (isl9112) ? fully protected for overcurrent, over-temperature and undervoltage ? small 3mmx3mm tdfn package applications ? regulated 3.3v from a single li-ion battery ? smart phones and tablet computers ? handheld devices ?point-of-load regulators related literature ? see an1648 ?isl9110irtnz/irt7z/irtaz-eval1z evaluation board user guide? ? see an1647 ?isl9112irtnz/irt7z-eval1z evaluation board user guide? figure 1. typical application v out = 3.3v/1a vout 1 fb 12 c2 10f bat pg status outputs 8 7 pvin v in = 1.8v to 5.5v vin 5 6 mode en 10 9 c1 10f isl9110irtnz gnd pgnd 11 3 lx1 lx2 4 2 l1 2.2h i out (a) efficiency (%) 70 75 80 85 90 95 100 0.01 0.05 0.25 1.25 v in = 5v v in = 2.5v v in = 3v v out = 3.3v figure 2. efficiency june 16, 2011 fn7649.0
isl9110, isl9112 2 fn7649.0 june 16, 2011 block diagram pin configurations isl9110 (12 ld tdfn) top view isl9112 (12 ld tdfn) top view osc error amp pvin pwm control pvin monitor lx1 v ref ref reverse current vout 5 4 2 lx2 gate drivers & anti- shoot thru 6 vin thermal shutdown i 2 c current detect 1 vout monitor 9 en 12 fb 3 pgnd 11 gnd en en en en en en vout clamp 8 bat 10 mode/sync 7 8 scl sda 7 pg voltage prog. en soft discharge vout pvin pgnd fb gnd lx1 lx2 vin en mode 1 2 3 4 5 6 7 8 9 10 11 12 pg bat isl9110 pad scl sda isl9112 pad vout pvin pgnd fb gnd lx1 lx2 vin en mode 1 2 3 4 5 6 7 8 9 10 11 12 pin descriptions pin # isl9110 isl9112 description 1 vout vout buck/boost output. connect a 10f capacitor to pgnd. 2 lx2 lx2 inductor connection, output side. 3 pgnd pgnd power ground for high switching current. 4 lx1 lx1 inductor connection, input side. 5 pvin pvin power input. range: 1.8v to 5.5v. connect a 10f capacitor to pgnd. 6 vin vin supply input. range: 1.8v to 5.5v. 7pg -open drain output. provides output-power-good status. -scllogic input, i 2 c clock. 8bat -open drain output. provides input-power-good status. - sda logic i/o, open drain, i 2 c data. 9 en en logic input, drive high to enable device. 10 mode / sync mode / sync logic input, high for auto pfm mode. low for forced pwm operation. ext. clock sync input. range: 2.75mhz to 3.25mhz. 11 gnd gnd analog ground pin. 12 fb fb voltage feedback pin. pad pad pad exposed pad; connect to pgnd.
isl9110, isl9112 3 fn7649.0 june 16, 2011 ordering information part number (notes 3, 4) part marking v out (v) temp range (c) package pkg. dwg. # isl9110irtnz (notes 1, 2) gasa 3.3 -40 to +85 12 ld exposed pad 3x3 tdfn l12.3x3c isl9110irt7z (notes 1, 2) gata 5.0 -40 to +85 12 ld exposed pad 3x3 tdfn l12.3x3c ISL9110IRTAZ (notes 1, 2) gaua adj. -40 to +85 12 ld exposed pad 3x3 tdfn l12.3x3c isl9112irtnz (notes 1, 2) gava 3.3 -40 to +85 12 ld exposed pad 3x3 tdfn l12.3x3c isl9112irt7z (notes 1, 2) gawa 5.0 -40 to +85 12 ld exposed pad 3x3 tdfn l12.3x3c isl9110eval1z evaluation board isl9112irtnz-eval1z evaluation board notes: 1. add ?-t*? suffix for tape and reel. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb- free products are msl classified at pb-free peak reflow temperat ures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for isl9110 or isl9112 . for more information on msl please see techbrief tb363 . 4. the isl9110 and isl9112 can be special ordered with an y output voltage between 1.9v and 5.0v in 100mv steps.
isl9110, isl9112 4 fn7649.0 june 16, 2011 table of contents absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 recommended operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 analog specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 i 2 c interface timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 typical performance curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 internal supply and references. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 enable input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 soft discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 por sequence and soft-start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 short circuit protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 pg status output (isl9110 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 bat status output (isl9110 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 ultrasonic mode (isl9112 only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 external synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 buck-boost conversion topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 pwm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 pfm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 operation with vin close to vout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 output voltage programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 digital slew rate control (isl9112 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 register description (isl9112) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 i 2 c serial interface (isl9112) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 protocol conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 write operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 output voltage programming, adj. version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 feed-forward capacitor selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 non-adjustable version fb pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 pvin and vout capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 application example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 application example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 application example 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 recommended pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 the tdfn package requires additional pcb layout rules for the thermal pad . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 general powerpad design considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
isl9110, isl9112 5 fn7649.0 june 16, 2011 absolute maximum rating s thermal information pvin, vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v lx1, lx2 (note 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v fb (adjustable version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 2.7v fb (fixed v out versions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v gnd, pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 0.3v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v esd rating human body model (tested per jesd22-a114e) . . . . . . . . . . . . . . . . 3kv machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . 250v latch up (tested per jesd-78b; class 2, level a) . . . . . . . . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) 12 ld tdfn package (notes 5, 6) . . . . . . . 42 5.5 maximum junction temperature (plastic package) . . . . . . . . . . . .+125c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8v to 5.5v load current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0a to 1.2a caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 5. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 6. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 7. lx1 and lx2 pins can withstand switching transients of -1.5v for 100ns, and 7v for 20ms. analog specifications v vin = v pvin = v en = 3.6v, v out = 3.3v, l1 = 2.2h, c1 = c2 = 10f, t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. symbol parameter test conditions min (note 8) typ (note 9) max (note 8) units power supply v in input voltage range 1.8 5.5 v v uvlo vin undervoltage lockout threshold rising 1.725 1.775 v falling 1.550 1.650 v i vin vin supply current pfm mode, no external load on vout (note 10) 35 60 a i sd vin supply current, shutdown en = gnd, v in = 3.6v 0.05 1.0 a output voltage regulation v out output voltage range ISL9110IRTAZ, i out = 100ma 1.00 5.20 v isl9112, i out = 100ma 1.90 5.00 v output voltage accuracy v in = 3.7v, v out = 3.3v, i out = 0ma, pwm mode -2 +2 % v in = 3.7v, v out = 3.3v, i out = 1ma, pfm mode -3 +4 % v fb fb pin voltage regulation for adjustable output version 0.79 0.80 0.81 v i fb fb pin bias current for adjustable output version 1 a v out / v in line regulation, pwm mode i out = 500ma, v out = 3.3v, mode = gnd, v in step from 2.3v to 5.5v 0.005 mv/mv v out / i out load regulation, pwm mode v in = 3.7v, v out = 3.3v, mode = gnd, i out step from 0ma to 500ma 0.005 mv/ma v out / v i line regulation, pfm mode i out = 100ma, v out = 3.3v, mode = vin, v in step from 2.3v to 5.5v 12.5 mv/v v out / i out load regulation, pfm mode v in =3.7v, v out = 3.3v, mode = vin, i out step from 0ma to 100ma 0.4 mv/ma v clamp output voltage clamp rising, v in = 3.6v 5.25 5.95 v output voltage clamp hysteresis v in = 3.6v 400 mv
isl9110, isl9112 6 fn7649.0 june 16, 2011 dc/dc switching specifications f sw oscillator frequency 2.25 2.50 2.75 mhz t onmin minimum on time 80 ns i pfetleak lx1 pin leakage current -1 1 a i nfetleak lx2 pin leakage current -1 1 a soft-start and soft discharge t ss soft-start time time from when en signal asserts to when output voltage ramp starts. 1ms time from when output voltage ramp starts to when output voltage reaches 95% of its nominal value with device operating in buck mode. v in = 4v, v out = 3.3v, i o = 200ma 1ms time from when output voltage ramp starts to when output voltage reaches 95% of its nominal value with device operating in boost mode. v in = 2v, v out = 3.3v, i o = 200ma 2ms r dischg vout soft-discharge on-resistance v in = 3.6v, en < vil 120 power mosfet r dson_p p-channel mosfet on-resistance v in = 3.6v, i o = 200ma 0.12 0.17 v in = 2.5v, i o = 200ma 0.15 0.23 r dson_n n-channel mosfet on-resistance v in = 3.6v, i o = 200ma 0.10 0.15 v in = 2.5v, i o = 200ma 0.13 0.23 i pk_lmt p-channel mosfet peak current limit v in = 3.6v 2.0 2.4 2.8 a pfm/pwm transition load current threshold, pfm to pwm v in = 3.6v, v out = 3.3v 200 ma load current threshold, pwm to pfm v in = 3.6v, v out = 3.3v 75 ma external synchronization frequency range 2.75 3.25 mhz thermal shutdown 155 c thermal shutdown hysteresis 30 c battery monitor and power good comparators vt bmon battery monitor voltage threshold 1.85 2.0 2.15 v vh bmon battery monitor voltage hysteresis 100 mv t bmon battery monitor debounce time 25 s pg delay time (rising) 1ms pg delay time (falling) 20 s minimum supply voltage for valid pg signal en = vin 1.2 v pg rnglr pg range - lower (rising) percentage of programmed voltage 90 % pg rnglf pg range - lower (falling) percentage of programmed voltage 87 % pg rngur pg range - upper (rising) percentage of programmed voltage 112 % pg rnguf pg range - upper (falling) percentage of programmed voltage 110 % compliance voltage - pg, bat v in = 3.6v, i sink = 1ma 0.3 v analog specifications v vin = v pvin = v en = 3.6v, v out = 3.3v, l1 = 2.2h, c1 = c2 = 10f, t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. (continued) symbol parameter test conditions min (note 8) typ (note 9) max (note 8) units
isl9110, isl9112 7 fn7649.0 june 16, 2011 logic inputs i leak input leakage 0.05 1 a v ih input high voltage 1.4 v v il input low voltage 0.4 v analog specifications v vin = v pvin = v en = 3.6v, v out = 3.3v, l1 = 2.2h, c1 = c2 = 10f, t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. (continued) symbol parameter test conditions min (note 8) typ (note 9) max (note 8) units i 2 c interface timing specification for scl, and sda pins, unless otherwise noted. symbol parameter test conditions min (note 8) typ (note 9) max (note 8) units c pin pin capacitance (note 11) 15 pf f scl scl frequency (note 11) 400 khz t sp pulse width suppression time at sda and scl inputs any pulse narrower than the max spec is suppressed (note 11) 50 ns t aa scl falling edge to sda output data valid scl falling edge crossing v il , until sda exits the v il to v ih window (note 11) 900 ns t buf time the bus must be free before the start of a new transmission sda crossing v ih during a stop condition, to sda crossing v ih during the following start condition (note 11) 1300 ns t low clock low time measured at the v il crossings (note 11) 1300 ns t high clock high time measured at the v ih crossings (note 11) 600 ns t su:sta start condition set-up time scl rising edge to sda falling edge; both crossing v ih (note 11) 600 ns t hd:sta start condition hold time from sda falling edge crossing v il to scl falling edge crossing v ih (note 11) 600 ns t su:dat input data set-up time from sda exiting the v il to v ih window, to scl rising edge crossing v il (note 11) 100 ns t hd:dat input data hold time from sc l rising edge crossing v ih to sda entering the v il to v ih window (note 11) 0ns t su:sto stop condition set-up time from scl rising edge crossing v ih , to sda rising edge crossing v il (note 11) 600 ns t hd:sto stop condition hold time for read, or volatile only write from sda rising edge to scl falling edge; both crossing v ih (note 11) 1300 ns t dh output data hold time from scl falling edge crossing v il , until sda enters the v il to v ih window (note 11) 0ns t r sda and scl rise time from v il to v ih (note 11) 20 + 0.1 x cb 250 ns t f sda and scl fall time from v ih to v il (note 11) 20 + 0.1 x cb 250 ns cb capacitive loading of sda or scl total on-chip and off-chip (note 11) 10 400 pf rpu sda and scl bus pull-up resistor off-chip maximum is determined by t r and t f for cb = 400pf, max is about 2k ~2.5k for cb = 40pf, max is about 15k ~20k (note 11) 1k notes: 8. parameters with min and/or max limits are 100% tested at +25c , unless otherwise specified. te mperature limits established by characterization and are not production tested. 9. typical values are for t a = +25c and v in = 3.6v. 10. quiescent current measurements are taken when the output is not switching. 11. isl9112 only. limits established by char acterization and are not production tested.
isl9110, isl9112 8 fn7649.0 june 16, 2011 typical performance curves figure 3. efficiency vs output current, v out = 2v figure 4. efficiency vs output current, v out = 3.3v figure 5. efficiency vs output current, v out = 4v figure 6. maximum output current vs input voltage figure 7. pwm mode quiescent current, v out = 3.3v, no load figure 8. pfm mode quiescent current, v out = 3.3v, no load 70 75 80 85 90 95 100 0.01 0.05 0.25 1.25 i out (a) efficiency (%) v in = 5v v in = 4.5v v in = 2.5v v in = 3v v in = 2v v out = 2.0v v in = 4v i out (a) efficiency (%) 70 75 80 85 90 95 100 0.01 0.05 0.25 1.25 v in = 5v v in = 4.5v v in = 4v v in = 2.5v v in = 2v v out = 3.3v v in = 3v 70 75 80 85 90 95 100 0.01 0.05 0.25 1.25 i out (a) efficiency (%) v in = 5v v in = 4.5v v in = 2.5v v in = 3v v in = 2v v out = 4.0v v in = 4v 0.0 0.5 1.0 1.5 2.0 2.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 i out (a) v in (v) v out = 5v v out = 3.3v v out = 2v 4 5 6 7 8 9 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 quiescent current (ma) v in (v) -40c 0c +25c +85c v out = 3.3v 30 35 40 45 50 55 60 1.5 2.5 3.5 4.5 5.5 -40c 0c +25c +85c v out = 3.3v quiescent current (a) v in (v)
isl9110, isl9112 9 fn7649.0 june 16, 2011 figure 9. steady state transition fr om buck to boost figure 10. steady st ate transition from boost to buck figure 11. steady state v in near v out figure 12. input transient figure 13. transient load response figure 14. transient load response typical performance curves (continued) lx1 5v/div 5v/div lx2 50mv/div vout 0.5a/div current inductor 400s/div v in = 4.5v 2.5v v out = 3.3v i out = 500ma lx1 5v/div 5v/div lx2 50mv/div vout 0.5a/div current inductor 400s/div v in = 2.5v 4.5v v out = 3.3v i out = 500ma lx1 2v/div 2v/div lx2 50mv/div vout 0.5a/div current inductor 400ns/div v in = 3.6v v out = 3.3v i out = 0.6a 50mv/div vout 2v/div vin 50s/div v in = 4.5v 2.5v 4.5v v out = 3.3v i out = 400ma 0.1v/div vout 0.5a/div current inductor 100s/div lx1 5v/div 5v/div lx2 v in = 2v v out = 3.3v i out = 0a to 0.4a lx1 5v/div 5v/div lx2 0.1v/div vout 0.5a/div current inductor 100s/div v in = 3.6v v out = 3.3v i out = 0a to 1a
isl9110, isl9112 10 fn7649.0 june 16, 2011 figure 15. switching waveforms, boost mode figure 16. switching waveforms, buck mode figure 17. nfet r ds(on) vs input voltage figure 18. pfet r ds(on) vs input voltage figure 19. v ref vs temperature, t a = -40c to +85c figure 20. output voltage vs v in voltage (v out = 3.3v) typical performance curves (continued) lx1 2v/div 2v/div lx2 10mv/div vout 0.5a/div current inductor 400ns/div v in = 2.5v v out = 3.3v i out = 500ma lx1 5v/div 5v/div lx2 10mv/div vout 0.5a/div current inductor 400ns/div v in = 4.5v v out = 3.3v i out = 1a 0.00 0.05 0.10 0.15 0.20 0.25 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -40c 0c +40c +85c r ds(on) ( ? ) v in (v) 0.00 0.05 0.10 0.15 0.20 0.25 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -40c 0c +40c +85c r ds(on) ( ? ) v in (v) 0.790 0.795 0.800 0.805 0.810 -40-20 0 2040608010 0 v ref (v) temperature (c) 3.270 3.275 3.280 3.285 3.290 1.5 2.5 3.5 4.5 5.5 i out = 0.1a (pfm) no load (pfm) i out = 1.2a (pwm) i out = 0.8a (pwm) i out = 0.4a (pwm) v out (v) v in (v)
isl9110, isl9112 11 fn7649.0 june 16, 2011 figure 21. soft-start, v in = 4v, v out = 3.3v figure 22. soft-start, v in = 2v, v out = 3.3v figure 23. output voltage vs load current (v in = 2.5v, v out = 3.3v, auto pfm/pwm mode) figure 24. output voltage vs load current (v in = 4.5v, v out = 3.3v, auto pfm/pwm mode) figure 25. output soft-discharge figure 26. digital slew operation (isl9112) typical performance curves (continued) lx1 2v/div 2v/div lx2 2v/div vout 2v/div en 400s/div v in = 4v v out = 3.3v i out = 200ma lx1 2v/div 2v/div lx2 2v/div vout 2v/div en 400s/div v in = 2v v out = 3.3v i out = 200ma 3.280 3.285 3.290 3.295 3.300 3.305 3.310 3.315 0.00.10.20.30.40. 5 v out (v) i out (ma) load current rising load current falling 3.280 3.285 3.290 3.295 3.300 3.305 3.310 0.0 0.1 0.2 0.3 0.4 0. 5 v out (v) i out (ma) load current rising load current falling 1v/div vout 1v/div en 4ms/div v in = 3.7v v out = 3.3v 200mv/div vout 2v/div scl 1ms/div 2v/div sda v in = 5v v out = 3.0v 4.0v 3.0v slewrate = 0b111
isl9110, isl9112 12 fn7649.0 june 16, 2011 functional description functional overview refer to the ?block diagram? on page 2. the isl9110, isl9112 implements a complete buck boost switching regulator, with pwm controller, internal switches, references, protection circuitry, and control inputs. the pwm controller automatically switches between buck and boost modes as necessary to maintain a steady output voltage, with changing input voltages and dynamic external loads. the isl9110 provides output-power-good and input-power-good open-drain status outputs on pins 7 and 8. in the isl9112, these pins are used for an i 2 c interface, allowing programmable output voltage and access to the ultrasonic mode and slew rate limit control bits. internal supply and references referring to the ?block diagra m? on page 2, the isl9110, isl9112 provides two power input pins. the pvin pin supplies input power to the dc/dc converter, while the vin pin provides operating voltage source required for stable v ref generation. separate ground pins (gnd and pgnd) are provided to avoid problems caused by ground shift due to the high switching currents. enable input a master enable pin en allows the device to be enabled. driving en low invokes a power-down mode, where most internal device functions, including input and output power good detection, are disabled. soft discharge when the device is disabled by driving en low, an internal resistor between vout and gnd is activated. this internal resistor has typical 120 ? resistance. por sequence and soft-start bringing the en pin high allows the device to power-up. a number of events occur during the start-up sequence. the internal voltage reference powers up, and stabilizes. the device then starts operating. there is a typical 1ms delay between assertion of the en pin and the start of switching regulator soft-start ramp. the soft-start feature minimizes output voltage overshoot and input inrush currents. during soft -start, the reference voltage is ramped to provide a ramping v out voltage. while output voltage is lower than approximately 20% of the target output voltage, switching frequency is reduced to a fraction of the normal switching frequency to aid in prod ucing low duty cycles necessary to avoid input inrush current sp ikes. once the output voltage exceeds 20% of the target voltage, switching frequency is increased to its nominal value. when the target output voltage is higher than the input voltage, there will be a transition from buck mode to boost mode during the soft-start sequence. at the time of this transition, the ramp rate of the reference voltage is decreased, such that the output voltage slew rate is decreased. this provides a slower output voltage slew rate. the v out ramp time is not constant for all operating conditions. soft-start into boost mode will take longer than soft-start into buck mode. the total soft-start time into buck operating mode is typically 2ms, whereas the typical soft-start time into boost mode operating mode is typically 3ms. increasing the load current will increase these typical soft-start times. overcurrent protection when the current in the p-channel mosfet is sensed to reach the current limit for 16 consecutiv e switching cycles, the internal protection circuit is triggered, and switching is stopped for approximately 20ms. the device then performs a soft-start cycle. if the external output overcurre nt condition exists after the soft-start cycle, the device will again detect 16 consecutive switching cycles reaching the peak current threshold. the process will repeat as long as the external overcurrent condition is present. this behavior is called ?hiccup mode?. short circuit protection the isl9110, isl9112 provides short-circuit protection by monitoring the feedback voltage. when feedback voltage is sensed to be lower than a certai n threshold, the pwm oscillator frequency is reduced in order to protect the device from damage. the p-channel mosfet peak current limit remains active during this state. undervoltage lockout the undervoltage lockout (uvlo) feature prevents abnormal operation in the event that the supply voltage is too low to guarantee proper operation. when the vin voltage falls below the uvlo threshold, the re gulator is disabled. pg status output (isl9110 only) an open drain output-power-good signal is provided in the isl9110. an internal window comp arator is used to detect when vout is significantly higher or lower than the target output voltage. the pg output will be driven low when sensed vout voltage is outside of this ?power good? window. when vout voltage is inside the ?power good ? window, the pg pin goes hi-z. the pg detection circuit detects this condition by monitoring voltage on the fb pin. hysteresis is provided for the upper and lower pg thresholds to avoid oscillation of the pg output. bat status output (isl9110 only) the isl9110 provides an open drain input-power-good status output. the bat status pin will be driven low when vin rises above the vt bmon threshold. the bat status output goes hi-z when v bat falls below the vt bmon threshold. hysteresis is provided for the vt bmon threshold to avoid oscillation of the bat output. ultrasonic mode (isl9112 only) the isl9112 provides an ultrason ic mode that can be enabled through i 2 c control by setting the ultra bit in the control register. in ultrasonic mode, the pfm switch ing frequency is forced to be above the audio frequency range. this ultrasonic mode applies only to pfm mode operation. with the ultra bit set to ?1?, pfm mode switching frequency is forced
isl9110, isl9112 13 fn7649.0 june 16, 2011 well above the audio frequency range (f sw becomes typically 60khz). this mode of operation, however, reduces the efficiency at light load. thermal shutdown a built-in thermal protection feature protects the isl9110, isl9112 if the die temperature reaches +155c (typical). at this die temperature, the regulator is completely shut down. the die temperature continues to be moni tored in this thermal-shutdown mode. when the die temperature falls to +125c (typical), the device will resume normal operation. when exiting thermal shutdown , the isl9110, isl9112 will execute its soft-start sequence. external synchronization an external sync feature is provid ed. applying a clock signal with a frequency between 2.75mhz and 3.25mhz at the en/sync input forces the isl9110, isl9112 to synchronize to this external clock. the en/sync input supports standard logic levels. buck-boost conversion topology the isl9110, isl9112 operates in either buck or boost mode. when operating in conditions wh ere vin is close to vout, the isl9110 alternates between buck and boost mode as necessary to provide a regulated output voltage. figure 27 shows a simplified di agram of the internal switches and external inductor. pwm operation in buck pwm mode, switch d is continuously closed, and switch c is continuously open. switches a and b operate as a synchronous buck converter when in this mode. in boost pwm mode, switch a remains closed and switch b remains open. switches c and d operate as a synchronous boost converter when in this mode. pfm operation during pfm operation in buck mode, switch d is continuously closed, and switch c is continuously open. switches a and b operate in discontinuous mo de during pfm operation. during pfm operation in boos t mode, the isl9110, isl9112 closes switch a and switch c to ramp up the current in the inductor. when inductor current reaches a certain threshold, the device turns off switches a and c, then turns on switches b and d. with switches b and d closed, output voltage increases as the inductor current ramps down. in most operating conditions, ther e will be multiple pfm pulses to charge up the output capacito r. these pulses continue until v out has achieved the upper threshold of the pfm hysteretic controller. switching then stops, and remains stopped until v out decays to the lower threshold of the hysteretic pfm controller. operation with vin close to vout when the output voltage is close to the input voltage, the isl9110, isl9112 will rapidly an d smoothly switch from boost to buck mode as needed to maintain the regulated output voltage. this behavior provides excellent efficiency and very low output voltage ripple. output voltage programming the isl9110 is available in fixed and adjustable output voltage versions. to use the fixed output version, the vout pin must be connected directly to fb. in the adjustable output voltage version (ISL9110IRTAZ), an external resistor divider is required to program the output voltage. the fb pin has very low input leakage current, so it is possible to use large value resistors (e.g. r1 = 1m ? and r2 = 324k ? ) in the resistor divider connected to the fb input. the isl9112 is available in a fixed output version only. the factory programmed output voltage can be changed via the i 2 c interface. details about the isl9112 programmable vout voltage can be found in the section ?register description (isl9112)? on page 13. digital slew rate control (isl9112 only) when changing voltages using the i 2 c interface, the isl9110 can be programmed to control the rate of voltage increase or decrease as it transi tions from one voltage setting to the next. the default configuration disables this digital slew rate feature. to enable the slew rate feature, an i 2 c command is sent to the isl9112, changing the value of th e slewrate bit field to a value other than 0b000. details about th e digital slew rate settings can be found in table 3. register description (isl9112) the isl9112 has a two i 2 c accessible control registers that are used to set output voltage, operating mode, and digital slew rate. these registers can be read and written to at any time that the isl9112 is enabled. attempts to communicate with the isl9112 via its i 2 c interface when the isl9112 is disabled (en = low) are not supported. figure 27. buck boost topology 5 pvin 1vout 4 2 switch a switch d switch b switch c lx1 lx2 l1
isl9110, isl9112 14 fn7649.0 june 16, 2011 bits dcdout[4:0] set the output voltage, as shown in equation 1 and table 2. the isl9112 output voltage range is 1.9v to 5.0v. a safety mechanism is provided to prevent unintentional changes to the output voltage by errant host software. the msb of the control register (i2cen bit, see table 1) mu st be set to ?1? in order for the isl9112 to recognize the i 2 c command as valid. if a value of ?0? is written to this bit, the i 2 c command is ignored, and output voltage and operating mode will revert to the factory programmed default (3.3v for isl9112irtnz; 5v for isl9112irt7z). i 2 c serial interface (isl9112) the isl9112 supports a bi-direction al bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is the master and the device being controlled is the slave. the master always initiates data transfers and provides the clock for both transmit and rece ive operations. therefore, the isl9112 operates as a slave device in all applications. all communication over the i 2 c interface is conducted by sending the msb of each byte of data first. protocol conventions data states on the sda line can change only during scl low periods. sda state changes duri ng scl high are reserved for indicating start and stop conditions (see figure 28). upon power-up of the isl9112, the sda pin is in the input mode. table 1. register address 0x00: voltage control bit name type reset description 4:0 dcdout r/w 00000 v out programming. see table 2. 5 ultra r/w 0 ultrasonic mode select. not applicable in forced pwm mode: 0: ultrasonic feature disabled 1: ultrasonic feature enabled 6 reserved r/w 0 7 i2cen r/w 0 i 2 c programming enable bit: 0: device ignores i 2 c command, and uses last programmed dcdout and ultra settings; or if no i 2 c communication has occurred since por, the factory programmed default dcdout and ultra settings are used. 1: device uses the i 2 c programmed dcdout and ultra settings. table 2. dcdout[4:0] value vs output voltage dcdout[4:0] output voltage (v) 0b00000 1.9 0b00001 2.0 0b00010 2.1 0b00011 2.2 0b00100 2.3 0b00101 2.4 0b00110 2.5 0b00111 2.6 0b01000 2.7 0b01001 2.8 0b01010 2.9 0b01011 3.0 0b01100 3.1 0b01101 3.2 0b01110 3.3 0b01111 3.4 0b10000 3.5 0b10001 3.6 v out 1.9v n 0.1v ? () + where n = 0 to 31 , = (eq. 1) 0b10010 3.7 0b10011 3.8 0b10100 3.9 0b10101 4.0 0b10110 4.1 0b10111 4.2 0b11000 4.3 0b11001 4.4 0b11010 4.5 0b11011 4.6 0b11100 4.7 0b11101 4.8 0b11110 4.9 0b11111 5.0 table 3. register address 0x01: slew rate control bit name type reset description 2:0 slewrate r/w 000 slew rate control (typ), expressed as s per lsb change in dcdout value: 0b000 = 0s/ lsb 0b001 = 1.5s/ lsb 0b010 = 3.1s/ lsb 0b011 = 6.3s/ lsb 0b100 = 12.5s/ lsb 0b101 = 25s/ lsb 0b110 = 50s/ lsb 0b111 = 100 / lsb 7:3 reserved r/w 00000 table 2. dcdout[4:0] value vs output voltage (continued) dcdout[4:0] output voltage (v)
isl9110, isl9112 15 fn7649.0 june 16, 2011 all i 2 c interface operations must be gin with a start condition, which is a high to low transition of sda while scl is high. the isl9112 continuously monitors the sda and scl lines for the start condition and does not respond to any command until this condition is met (see figure 28) . a start condition is ignored during the power-up sequence and when en input is low. all i 2 c interface operations must be terminated by a stop condition, which is a low to high transition of sda while scl is high (see figure 28). a stop condition at the end of a write operation initiates the reconfigur ation of the isl9112?s voltage feedback loop as necessary to provide the programmed output voltage. an ack, acknowledge, is a software convention used to indicate a successful data transfer. the tr ansmitting device, either master or slave, releases the sda bus after transmitting eight bits. during the ninth clock cycle, the receiver pulls the sda line low to acknowledge the reception of the eight bits of data (see figure 29). the isl9112 responds with an ack after recognition of a start condition followed by a valid iden tification byte, and once again after successful receipt of a re gister address byte. the isl9112 also responds with an ack after receiving a data byte of a write operation. the master must respond with an ack after receiving a data byte of a read operation. a valid identification byte co ntains 0b0011100 as the seven msbs, corresponding to the isl9112 i 2 c slave address. the lsb of the identification byte is the read/write bit. its value is ?1? for a read operation, and ?0? for a write operations (see table 4). write operation a write operation requires a start condition, followed by a valid identification byte (containing the slave address with the r/w bit set to 0), a valid register address byte, a data byte, and a stop condition. after each of the three bytes, the isl9112 responds with an ack. the master will then send a stop to complete the command. stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte and its associated ack signal. if a stop condition is issued in the middle of a data byte, or before 1 full data byte + ack is sent, then the isl9112 will ignore the comm and, and not change output voltage or other settings. read operation a read operation is shown in figure 31. it consists of 4 bytes. the host generates a start condition, then transmits an identification byte (containing the slave address with the r/w bit set to 0). the isl9112 responds with an ack. the host then transmits the register address byte, and the is l9112 responds with another ack. the host then generates a repeat start condition, or a stop condition followed by a start condition. the host then transmits an identification byte (containin g the slave address with the r/w bit set to 1). the isl9112 responds with an ack, indicating it is ready to begin providing the requested data. the isl9112 then transmits the data byte by asserting control of the sda pin while the host generates clock pulses on the scl pin. when transmission of the data byte is complete, the host generates a nack condition followed by a stop condition. this completes the i 2 c read operation. the isl9112 register map supports only one register, at register address 0x00. attempts to read other register addresses are not supported, and should not be attempted. similarly, i 2 c block reads and writes are not supported by the isl9112. the isl9112 has only one register to read or write, therefore block reads and writes are not necessary. table 4. identification byte format 0 011100r/w (msb) (lsb) sda scl start data data stop stable change data stable figure 28. valid data changes, start and stop conditions
isl9110, isl9112 16 fn7649.0 june 16, 2011 sda output from transmitter sda output from receiver 8 1 9 start ack scl from master high impedance figure 29. acknowledge response from receiver high impedance figure 30. i 2 c register write protocol s 0 a p data byte r/w a system host isl9112 a ? acknowledge n ? not acknowledge s ? start p ? stop a isl9112 i 2 c write protocol dcdv1 (5 bits) ultra warn i2c_en 00000000 register address = 0x00 i 2 c slave 7-bit address 0011100 figure 31. i 2 c register read protocol s 0 a p r/w s 1 r/w n data byte a a isl9112 i 2 c read protocol #1 dcdv1 (5 bits) ultra warn i2c_en s 0 a p r/w s 1 r/w n data byte a a isl9112 i 2 c read protocol #2 dcdv1 (5 bits) ultra warn i2c_en p 00000000 00000000 register address = 0x00 register address = 0x00 i 2 c slave 7-bit address i 2 c slave 7-bit address i 2 c slave 7-bit address i 2 c slave 7-bit address 0011100 0011100 0011100 0011100 system host isl9112 a ? acknowledge n ? not acknowledge s ? start p ? stop
isl9110, isl9112 17 fn7649.0 june 16, 2011 applications information component selection the isl9112 and the fixed-output versions of the isl9110 require only three external power components to implement the buck boost converter: an inductor, an input capacitor, and an output capacitor. the adjustable isl9110 versio ns require three additional components to program the output voltage. two external resistors program the output volt age, and a small capacitor is added to improve stab ility and response. an optional input supply filtering capacitor (?c3? in figure 32) can be used to reduce the supply noise on the vin pin, which provides power to the internal reference. in most applications, this capacitor is not needed. output voltage programming, adj. version setting and controlling the output voltage of the ISL9110IRTAZ (adjustable output version) can be accomplished by selecting the external resistor values. equation 2 can be used to derive the r1 and r2 resistor values: when designing a pcb, include a gnd guard band around the feedback resistor network to reduce noise and improve accuracy and stability. resistors r1 and r2 should be positioned close to the fb pin. feed-forward capacitor selection a small capacitor in parallel with resistor r1 is required to provide the specified load and line regulation. the suggested value of this capacitor is 56pf for r1 = 1m . an npo type capacitor is recommended. non-adjustable version fb pin connection the fixed output versions of the isl9110 and the i 2 c-adjustable isl9112 do not require external resistors or a capacitor on the fb pin. simply connect vout to fb, as shown in figure 33. inductor selection an inductor with high frequency core material (e.g. ferrite core) should be used to minimize core losses and provide good efficiency. the inductor must be able to handle the peak switching currents without saturating. a 10 h inductor with 2.4a saturation current rating is recommended. select an inductor with low dcr to provide good efficiency. in applications where radiated noise must be minimized, a toroidal or shielded inductor can be used. pvin and vout capacitor selection the input and output capacitors sh ould be ceramic x5r type with low esl and esr. the recommended input capacitor value is 10 f. the recommended vout capacitor value is 10 f to 22 f. figure 32. typical ISL9110IRTAZ application v out = 3.3v/1a vout 1 fb 12 c2 10f r1 r2 1m 324k bat pg status outputs 8 7 pvin v in = 1.8v to 5.5v c3 0.1f vin 5 6 mode en 10 9 c1 10f isl9110 gnd pgnd 11 3 lx1 lx2 4 2 l1 2.2h c4 56pf v out 0.8v 1 r1 r2 ------- + ?? ?? ? = (eq. 2) table 5. inductor vendor information manufacturer series website coilcraft lps4018 www.coilcraft.com murata lqh44p www.murata.com taiyo yuden nrs4018 nrs5012 www.t-yuden.com sumida cdrh3d23/hp cdrh4d22/hp www.sumida.com toko dem3518c www.toko.co.jp table 6. capacitor vendor information manufacturer series website avx x5r www.avx.com murata x5r www.murata.com taiyo yuden x5r www.t-yuden.com tdk x5r www.tdk.com figure 33. typical isl9110irtnz application pvin v in = 1.8v to 5.5v c3 v out = 3.3v/1a isl9112 0.1f vin 5 6 mode en 10 9 lx1 lx2 4 2 l1 2.2h vout 1 fb 12 c2 10f sda scl i 2 c bus 8 7 gnd pgnd 11 3 c1 10f
isl9110, isl9112 18 fn7649.0 june 16, 2011 application example 1. an application using the fixed-output isl9110irtnz is shown in figure 34. this application requires only three external components. application example 2. an application requiring v out = 3.0v, using the adjustable-output ISL9110IRTAZ is shown in figure 35. this application requires six external components. application example 3. an application requiring v out =3.3v, using the i 2 c-controllable isl9112irtnz is shown in figure 36. this application requires three external components. outp ut voltage can be changed via i 2 c control. recommended pcb layout correct pcb layout is critical for proper operation of the isl9110. the input and output capacitors sh ould be positioned as closely to the ic as possible. the grou nd connections of the input and output capacitors should be kept as short as possible, and should be on the component layer to avoid problems that are caused by high switching currents flowing through pcb vias. the tdfn package requires additional pcb layout rules for the thermal pad the thermal pad is electrically connected to the pgnd supply. its primary function is to provide heat sinking for the ic. however, because of the connection to pgnd, the thermal pad must be tied to the gnd supply to prevent unwanted current flow to the thermal pad. maximum ac performance is achieved if the thermal pad is attached to a dedicated ground layer in a multi-layered pc board. the thermal pad requirements are proportional to power dissipation and ambient temperature. a dedicated layer eliminates the need for indivi dual thermal pad area. when a dedicated layer is not possible, an isolated thermal pad on another layer should be used. pad area requirements should be evaluated on a case by case basis. general powerpad design considerations the following is an example of how to use vias to remove heat from the ic. v out = 3.3v/1a vout 1 fb 12 c2 10f bat pg status outputs 8 7 pvin v in = 1.8v to 5.5v vin 5 6 mode en 10 9 c1 10f isl9110irtnz gnd pgnd 11 3 lx1 lx2 4 2 l1 2.2h figure 34. typical isl9110irtnz application v out = 3.0v/1a vout 1 fb 12 c2 10f r1 r2 1m 365k bat pg status outputs 8 7 pvin v in = 1.8v to 5.5v vin 5 6 mode en 10 9 c1 10f ISL9110IRTAZ gnd pgnd 11 3 lx1 lx2 4 2 l1 2.2h c4 56pf figure 35. typical ISL9110IRTAZ application pvin v in = 1.8v to 5.5v v out = 3.3v/1a isl9112irtnz vin 5 6 mode en 10 9 lx1 lx2 4 2 l1 2.2h vout 1 fb 12 c2 10f sda scl i 2 c bus 8 7 gnd pgnd 11 3 c1 10f figure 36. typical isl9112irtnz application figure 37. recommended pcb layout figure 38. pcb via pattern
isl9110, isl9112 19 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7649.0 june 16, 2011 for additional products, see www.intersil.com/product_tree we recommend that you fill the thermal pad area with vias. fill the thermal pad area with vias that are spaced 3x their radius (typically), center-to-center, from each other. keep the vias small but not so small that their insi de diameter prevents solder wicking through the holes during reflow. it is important that the vias have a low thermal resistance for efficient heat transfer. do not use ?thermal relief? patterns to connect the vias to the ground plane. instead use a solid connection with no gaps for improved thermal performance. products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. *for a complete listing of applications, related documentation an d related parts, please see the respective device information page on intersil.com: isl9110 , isl9112 to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for inform ational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change june 16, 2011 fn7649.0 initial release.
isl9110, isl9112 20 fn7649.0 june 16, 2011 package outline drawing l12.3x3c 12 lead thin dual flat no-lead plastic package (0.4mm pitch) rev 0, 11/09 located within the zone indicated. the pin #1 indentifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 id entifier is optional, but must be between 0.15mm and 0.25mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to asme y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view 2.450.1 1.700.1 12x 0.40 12x 0.20 0.40 1.70 (10 x0.40) (12 x0.20) (12 x0.20) (12 x0.40) 2.45 (4x) 0.15 index area pin 1 a 3.00 b 3.00 pin #1 b 0.10 ma c 4 0 . 75 c seating plane base plane 0.08 0.10 see detail "x" c c 0 . 00 min. 0 . 05 max. 0 . 2 ref c 5 6 6 0.20 0.05 package outline index area

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